Presuming it makes it to market, a multi-tiled GPU– basically multiple GPUs in a single plan– would be a significant achievement for Intel. GPUs are infamously bandwidth-hungry due to the requirement to shovel data around between cores, caches, and command frontends, which makes them non-trivial to divide up in a chiplet/tiled fashion. Even if Intel can only use this type of multi-tile scalability for compute work, that would have a substantial effect on what sort of performance a single GPU bundle can achieve, and how future servers might be developed.
Developed to be a scalable chip architecture, Xe-HP is set to be available with one, 2, or four tiles. And while Intel has yet to divulge too much in the method of information on the architecture, based on their packaging disclosures it appears like the company is using their EMIB tech to wire up the GPU tiles, along with the GPUs on-package HBM memory.
At last weeks Intel Architecture Day, Intels primary designer, Raja Koduri, briefly held up the tiniest member of the businesss upcoming Xe-HP series of server CPUs, the one tile setup. Now, just a couple of days later on, he has actually upped the ante by revealing off the biggest, four tile setup.
